The present invention relates to a stack package, and more particularly, to a stack package which is realized using a through-via interconnection plug and a method for manufacturing the same.
In the semiconductor industry, packaging technology for an integrated circuit has continuously been developed to meet the demand toward miniaturization and mounting reliability. Recently, as the miniaturization and high functionality of electric/electronic products are required, various techniques have been disclosed in the art.
The term “stack” in the semiconductor industry means a vertical stand or pile of at least two semiconductor chips or semiconductor packages, one atop the other. By using a stack of packages, in the case of a memory device for example, it is possible to produce a product having a memory capacity which is two times greater than that obtained through semiconductor integration processes. Also, a stack package provides advantages not only through an increase in memory capacity but also in view of a mounting density and mounting area utilization efficiency. Due to this fact, researches and development for a stack package have been accelerated.
As an example of a stack package, a stack package structure has been disclosed in the art, in which through-via interconnection plugs are formed in chips to physically and electrically connect upper and lower chips with each other. A prior art method for manufacturing a stack package using through-via interconnection plugs is as described below.
A hole is defined in a predetermined portion of each chip at a wafer level through an etching process. After an oxide layer is formed on the surface of the hole, a connection plug made of a metal is formed in the hole. The connection plug made of a metal is formed by electro-plating. A seed metal layer made of a conductive metal is deposited over the oxide layer through CVD or PVD. An electro-plating process is implemented to fill the hole with a metal. Then, in order to expose an end of the connection plug which faces the backside of the wafer, the backside of the wafer is back-grinded.
After the wafer is sawed and separated into individual chips, at least two such chips can be stacked on a substrate having a circuit pattern using the connection plugs. If the stack is completed in this way, the upper surface of the substrate including the stacked chips is molded, and solder balls are mounted on the lower surface of the substrate, by which the manufacture of a stack package is completed.
In this type of conventional stack package in which the chips are connected with each other using the through-via interconnection plugs, when performing a thermal cycle reliability test, cracks and disconnections are likely to be produced at joint regions between the connection plugs, because of thermal expansion and contraction. As a result, joint reliability deteriorates. Since joint reliability deteriorates, device reliability deteriorates.